Magnetoelectronic devices, spin electronic devices, and spintronic devices are synonymous terms for devices that make use of effects predominantly caused by electron spin. Magnetoelectronics are used in numerous information devices to provide non-volatile, reliable, radiation resistant, and high-density data storage and retrieval. The numerous magnetoelectronics information devices include, but are not limited to, Magnetoresistive Random Access Memory (MRAM), magnetic sensors, and read/write heads for disk drives.
Typically an MRAM includes an array of magnetoressistive memory elements. Each magnetoresistive memory element typically has a structure that includes multiple magnetic layers separated by various non-magnetic layers, such as a magnetic tunnel junction (MTJ), and exhibits an electrical resistance that depends on the magnetic state of the device. Information is stored as directions of magnetization vectors in the magnetic layers. Magnetization vectors in one magnetic layer are magnetically fixed or pinned, while the magnetization direction of another magnetic layer may be free to switch between the same and opposite directions that are called “parallel” and “antiparallel” states, respectively. Corresponding to the parallel and antiparallel magnetic states, the magnetic memory element has low (logic “0” state) and high (logic “1” state) electrical resistance states, respectively. Accordingly, a detection of the resistance allows a magnetoresistive memory element, such as an MTJ device, to provide information stored in the magnetic memory element. There are two completely different methods used to program the free layer: field switching and spin-torque switching. In field-switched MRAM, current carrying lines adjacent to the MTJ bit are used to generate magnetic fields that act on the free layer. In spin-torque MRAM, switching is accomplished with a current pulse through the MTJ itself. The angular momentum carried by the spin-polarized tunneling current causes reversal of the free layer, with the final state (parallel or antiparallel) determined by the polarity of the current pulse. A reset current pulse will cause the final state to be parallel or logic “0”. A set current pulse, in the opposite polarity of reset current pulse, will cause the final state to be antiparallel or logic “1”. Spin-torque transfer is known to occur in MTJ devices and giant magnetoresistance devices that are patterned or otherwise arranged so that the current flows substantially perpendicular to the interfaces, and in simple wire-like structures when the current flows substantially perpendicular to a domain wall. Any such structure that exhibits magnetoresistance has the potential to be a spin-torque magnetoresistive memory element.
Spin-torque MRAM (ST-MRAM), also known as spin-torque-transfer RAM (STT-RAM), is an emerging memory technology with the potential for non-volatility with unlimited endurance and fast write speeds at much higher density than field-switched MRAM. Since ST-MRAM switching current requirements reduce with decreasing MTJ dimensions, ST-MRAM has the potential to scale nicely at even the most advanced technology nodes. However, increasing variability in MTJ resistance and sustaining relatively high switching currents through bitcell select devices in both current directions can limit the scalability of ST-MRAM. The write current is typically higher in one direction compared to the other, so the select device must be capable of passing the larger of the two currents. In addition, ST-MRAM switching current requirements increase as the write current pulse duration is reduced. Because of this, the smallest ST-MRAM bitcell approach may require relatively long switching times.
Data stored in memory is defined in banks. A rank is a plurality of banks in a first direction (column) and a channel is a plurality of banks in a second direction (row). A process for accessing the memory comprises several clock cycles required for row and column identification and a read or write operation. The bandwidth for the data transfer may comprise a row of many thousands of bits.
Access to a bank in a double data rate (DDR) memory generally includes an ACTIVATE operation, followed by several READ/WRITE operations and a PRECHARGE operation. The ACTIVATE operation opens a row (or page) of typically 1,000 or more bits. The READ/WRITE operation performs the reading or writing of columns, e.g., 128 bits, in the open row (or page). The PRECHARGE operation closes the row.
During the ACTIVATE operation, a page of data is read from the memory array and stored in local data-store latches for subsequent READ and WRITE operations to the local data-store latches. The ACTIVATE operation can be initiated by an ACTIVATE command or any other command that performs the same operation. READ or WRITE operations to the local data-store latches can occur at very high speed, for example every 5 ns. During a PRECHARGE operation, the data from local data-store latches are written back to the memory array, and as a result, that page is considered closed or not accessible without a new ACITVATE operation. The PRECHARGE operation can be initiated by a PRECHARGE or AUTO-PRECHARGE command or any other command that performs the same operation. During the PRECHARGE operation in ST-MRAM, current pulses to write the MTJs corresponding to the open row would be applied to write-back the data from the local data-store latches to ST-MRAM array.
To minimize power consumption during writes to memory array, a known majority detection and data state inversion scheme can be employed. According to a majority detection scheme, a majority state of the data is determined to be a first or second state. Either one of the first or second state may consume more power to write to the memory. If the majority state is determined to be the more power consuming state, all the data bit states may be inverted to the opposite state and written back to the memory. Thus, power consumption during write operation is reduced. However, the majority detection circuit may take some time, for example 5 ns to 10 ns, and would add to the memory write operation time. Majority detection time followed by ST-MRAM write current pulses, e.g., 10 nanoseconds or more, may not be suitable for completion during short PRECHARGE operation time.
It is desirable to add error correcting code (ECC) and error correction functionality to ST-MRAM memory to reduce memory error rate. Error correction functionality may further delay the access time to a memory. Therefore, it is desirable to provide a method of reading and writing ST-MRAM memory that employs ECC for reduced error rate, majority detection and inversion scheme for write power reduction, and accordingly manage the memory access delays in a high bandwidth memory system. Furthermore, other desirable features and characteristics of the exemplary embodiments will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.